Distinguished Engineer, Digital ASIC
Location
California + 2 moreAll locations: California, New York, Massachusetts
Posted
21 days ago
Salary
$240K / year
Job Description
Job Requirements
- Baseline skills/experiences/attributes:
- BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
- 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership.
- Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs.
- Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
- Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
- Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.
- Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP.
- Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.
- Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts).
- Ideally, you also have these skills/experiences/attributes (but it’s ok if you don’t!):
- Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths).
- Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.
- Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs.
- Values
- Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in…
- Patient-Centric Innovators: Our mission is THE mission.
- Empowered to Impact: Every voice matters.
- One Team, One Goal: Unity fuels progress.
- Growth Champions: We embrace challenges.
- Action-Oriented Achievers: We follow through, every time.
- Location
- Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers.
- For this role, location will depend on candidate qualifications and experience. This role may be based out of one of our U.S. offices, including:
- SF Bay Area
- Burlington, MA
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