We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, R...

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL ...

The engineer will be responsible for developing, implementing, and maintaining RTL verification environments using UVM or equivalent methodologies, and creating coverage-driven verification plans aligned with design specifications. Key tasks include developing test cases, analyzing simulation results, debugging issues with design engineers, and driving verification closure through coverage tracking.

The engineer will select and design optimal multi-die IC package types while performing detailed Signal Integrity and Power Integrity analyses for high-speed interfaces. Key tasks involve running complex simulations, defining package specifications, and collaborating cross-functionally with design and layout teams.