• Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs. • Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions. • Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals. • Define high-speed interconnect fabric, memory subsystems (DDR/HBM), and IO protocols (PCIe, CXL, UCIe). • Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation. • Drive architectural trade-off studies and lead design reviews. • Define advanced power management strategies including DVFS, power domains, and clock gating. • Mentor junior engineers and contribute to technical leadership across the organization.