• Help push the boundaries of what can run on our accelerator. • Design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. • Work side by side with hardware engineers to influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. • Create a compiler that makes complex algorithms practical to deploy while staying seamless for developers.