Cincinnatus is an enterprise staffing company that partners with leading technology companies to source and employ highly skilled professionals for full-time and long-term contingent roles. Cincinnatus serves as the employer of record for these engagements, providing W-2 employment, payroll, benefits, and compliance, while placing employees directly within client teams to work on high-impact initiatives. Roles hired through Cincinnatus are not project-based or freelance engagements. They are structured, role-based positions that typically involve full-time or fixed-term commitments, close collaboration with a client's internal teams, and integration into standard enterprise workflows. Cincinnatus is a legal entity separate from Mercor. While opportunities may be discovered through Mercor's platform, employment, onboarding, payroll, and benefits for these roles are administered by Cincinnatus. Equal Employment Opportunity Cincinnatus is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or any other legally protected characteristic. Cincinnatus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans throughout the job application process.
ASIC Power Engineer
Location
United States
Posted
2 days ago
Salary
$100 - $135 / hour
Seniority
Mid Level
Job Description
Role Description
- Perform PPA optimization with Fusion compiler to enhance ASIC efficiency.
- Conduct RTL and netlist level power analysis to improve power management.
- Execute post-processing and scripting on report log files for format conversion and data analysis.
- Setup, run, debug, and analyze reports of ASIC flows including Synthesis, PD, Power, and Timing.
- Implement blocks at RTL and UPF to optimize design processes.
- Document and communicate findings clearly to enhance team understanding.
Qualifications
- Must-Have:
- 10+ years of experience as an ASIC Power Engineer or CAD/Physical Design Engineer.
- Experience with power estimation tools and synthesis, including some physical design.
- Knowledge of power trade-offs in design and back end implementation.
- Hands-on experience in scripting and data analysis.
- Bachelor's degree in Electrical Engineering/Computer Science or equivalent experience.
- Preferred:
- Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
- Python, Perl (or similar) scripting and data-post-processing tools.
- Excel (or Matlab) for model fitting, data visualization, and analysis.
- Experience in low power design, tools, and methodologies including power intent UPF specifications.
- Silicon Power Characterization.
- Some power profiling experience at IP/SoC level.
Company Description
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.
Job Requirements
- Must-Have:
- 10+ years of experience as an ASIC Power Engineer or CAD/Physical Design Engineer.
- Experience with power estimation tools and synthesis, including some physical design.
- Knowledge of power trade-offs in design and back end implementation.
- Hands-on experience in scripting and data analysis.
- Bachelor's degree in Electrical Engineering/Computer Science or equivalent experience.
- Preferred:
- Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
- Python, Perl (or similar) scripting and data-post-processing tools.
- Excel (or Matlab) for model fitting, data visualization, and analysis.
- Experience in low power design, tools, and methodologies including power intent UPF specifications.
- Silicon Power Characterization.
- Some power profiling experience at IP/SoC level.
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