Senior ASIC Power Engineer

EngineerEngineerFull TimeRemoteTeam 10,001+Since 1993H1B SponsorCompany Site LinkedIn

Location

California

Posted

31 days ago

Salary

$136K - $218.5K / year

Bachelor Degree5 yrs expEnglishPython

Job Description

• Join the NVIDIA Power Architecture Group handling the full range of power-related activities including ASIC energy evaluation, power architecture, low power development, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's product lineup • Support power analysis efforts by aiding in the architecture, creation, verification, and correlation of power estimation models/tools for NVIDIA's products • Be part of the team that architects and builds system-level power features for optimizing the dynamic and leakage power dissipation for different use cases • Work on power verification which includes structural, functional, and power-aware verification of power features of NVIDIA products by developing test plans, writing test cases, building test bench components like monitors, assertions, and coverage points, and owning verification convergence across RTL, Gates, and Silicon • Validate the efficiency of the power features on silicon, conduct studies, and contribute to Performance/Watt improvement ideas • Help develop power management solutions and foster innovation in energy efficiency throughout NVIDIA's product portfolio.

Job Requirements

B.Tech./M.Tech (or equivalent experience)
Over 5 years of experience in power analysis, power development, power-aware verification, UPF methodologies, and power correlation
Solid understanding of all power aspects, including full-chip power modeling, transistor-level leakage, and dynamic characteristics in VLSI circuits
Strong fundamentals in digital build flow and Verilog (especially low power RTL development)
Familiarity with low power build techniques such as multi-VT, clock gating, power gating, voltage islands, and Dynamic Voltage-Frequency Scaling (DVFS)
Solid experience in power estimation methods, processes, and algorithms
Working experience with scripting languages like Python is a must
Prior experience writing SW-driven power virus tests and silicon debug is necessary
Experience in power supply and supply noise analysis and reduction is advantageous
Must be an excellent collaborator and prepared to work with international groups from varied cultural origins in a dynamic environment.