• Lead the design and development of high-performance, high-speed ADC and DAC architectures. • Lead the architecture definition and implementation of low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems. • Own the planning and execution of simulations for critical mixed-signal sub-systems at the transceiver level to ensure system performance and compliance. • Own the package design strategy, modeling, and cross-functional integration. • Lead cross-functional efforts to integrate circuits advanced FinFET-based SoCs, ensuring layout, parasitic, and floor planning alignment. • Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation. • Perform design optimization for power, area, and performance in advanced FinFET nodes. • Develop and maintain design documentation and support post-silicon bring-up and characterization. • Support your product through production and spaceflight. • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.