• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog. • Translate algorithmic and architectural specifications into synthesizable RTL. • Implement DSP functions such as filtering, FFT/IFFT, or beamforming. • Convert chip specifications into RTL using internal IPs and external IPs. • Design and develop RTL for interfaces, power management, clocking, reset, test & debug. • Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic. • Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration. • Contribute to block-level integration, synthesis, and timing closure. • Participate in design reviews, functional verification, and timing closure. • Participate in chip bring-up and lab validation of complex digital subsystems. • Support your product through production and spaceflight.