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Role Description

We are pleased to announce that Condor is seeking a skilled and personable Sr. DV Engineer to become a valuable member of our team. In this position, you will have the opportunity to investigate innovative strategies to enhance the performance of our high-performance RISC-V processors, with a focus on all functions within the CPU core and memory systems. You will work collaboratively with a talented team, including engineers from RTL design, verification, and software groups, to propose enhancements, optimizations, and features based on performance assessments and PPA impact.

• Architect and implement testbenches utilizing UVM-based methodologies
• Design and develop Verification Components using UVM-based techniques
• Conduct block-level verification to ensure optimal block performance and compliance with requirements
• Generate and execute verification plans based on specifications
• Define, implement, and analyze coverage metrics
• Architect and implement Formal Verification processes
• Create automation tools to streamline testing
• Perform testing for design performance evaluation

Qualifications

• A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science
• 8+ years of experience in Verification
• Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception
• In-depth knowledge of event-driven simulator-based modeling techniques
• Experience with low-power implementation (UPF)
• Familiarity with scripting languages such as Python, Ruby, or Perl
• A comprehensive understanding of chip and/or computer architecture

Requirements

• Strong written and verbal communication abilities
• Exceptional collaboration skills across sites and functions

Company Description

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry’s highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing.