• Own feature development from specification through RTL design, implementation, and synthesis. • Implement product features targeting both silicon and FPGA platforms. • Develop robust unit testbench infrastructure and contribute to verification strategies. • Design memory subsystems and integrate memory macros (SRAM, MRAM, etc.). • Integrate and interface vendor-provided IP with custom RTL designs. • Use industry-standard EDA tools across the full digital design flow (Cadence, Synopsys, Siemens/Mentor, ANSYS). • Collaborate with physical design to resolve RTL issues and ensure high-quality tape-out. • Partner with verification, software, and compiler teams to implement features that cross the hardware–software boundary, including support for Efficient’s dataflow ISA. • Produce high-quality design documentation and participate in design reviews. • Provide mentorship to junior engineers and contribute to best-practice development processes.