• Verify AI-related sophisticated ASIC designs & features with formal verification methods. • Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. • Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications. • Develop and implement advanced formal verification environments and methodologies for complex ASIC designs. • Train and coach junior engineers on formal techniques and standard processes; Help on methodology/FAQ documentation. • Support silicon bring-up and debug using formal methods where it applies.