Senior Design Verification Engineer

DesignerDesignerFull TimeRemoteTeam 11-50Since 2023Company Site LinkedIn

Location

Texas

Posted

17 days ago

Salary

Not specified

Bachelor Degree8 yrs expEnglishPerlPythonRuby

Job Description

• Architect and implement testbenches utilizing UVM-based methodologies • Design and develop Verification Components using UVM-based techniques • Conduct block-level verification to ensure optimal block performance and compliance with requirements • Generate and execute verification plans based on specifications • Define, implement, and analyze coverage metrics • Architect and implement Formal Verification processes • Create automation tools to streamline testing • Perform testing for design performance evaluation

Job Requirements

A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science
8+ years of experience in Verification
Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception
In-depth knowledge of event-driven simulator-based modeling techniques
Experience with low-power implementation (UPF)
Familiarity with scripting languages such as Python, Ruby, or Perl
A comprehensive understanding of chip and/or computer architecture